Semiconductor random access memories (RAMs) are typically formed of rowlines and columns crossing the rowlines. Capacitors adjacent each crossing of the rowlines and columns store charge, designating the data to be stored. The capacitors are switched to the columns in order to receive or discharge charge upon receipt of an appropriate voltage on the rowlines. The rowlines and columns are selected so as to read and write to particular capacitors by means of row (or X) decoders and column (or Y) decoders.
There are sometimes physical faults associated with the columns or associated elements. For this reason, RAMs usually contain redundant (spare) columns which involve the provision of extra memory elements and column circuitry. The extra memory and required redundant decoders to access that memory in place of defective columns uses valuable semiconductor chip area and decreases the area efficiency of the memory. As the occurrence of defective columns is a reality with which a chip manufacturer has to adapt to, various schemes have been devised to allow replacing faulty columns with redundant columns at manufacture time.
For example, in synchronous dynamic random access memories (SDRAMs), a first of these techniques utilizes an Y address comparator, wherein pre-decoded Y address signals (PYl:N) pass through fuses to generate redundant column enable signals (RCE) which is shown in FIG. 1. The fuses associated with the redundancy comparator, having inherent capacitance and resistance, which add an extra delay in the Y redundant path.
A second technique involves an Y address detector wherein Y address signals (AY(N01:0)) control NMOS gates that connect to a pre-charged node through fuses and each generate redundant column enable signals as shown in FIG. 2. When a Y address matches a fuse programming pattern, a column redundant enable signal (COL.sub.-- RED.sub.-- EN) is maintained high in order to indicate that the column corresponding to the current Y address will be replaced by a redundant one. Because of this redundancy detecting circuit, timing between the normal and the redundant column path is usually different. Additional logic circuits are required to adjust the timing difference, i.e. time delay circuit must be employed in the normal address path in order to compensate for the slower redundant path.
A further technique known as a shift replacement Y decoder utilizes fuses in the Y decoder. Generally, two Y select lines share one group of fuses. In order to replace a column, the column is simply disabled by blowing the fuse inside the Y decoder. Shifting the Y driver access for the defective block over to an adjacent driver completes replacement. An advantage of this system is that fuses are not connected in the column address path and, therefore, no difference in timing between the normal and redundant path exists. Furthermore, block replacement is possible (failed columns can be repaired in each block with different decoding of each block). A disadvantage of this system is that two adjacent Y select lines must be replaced at the same time making this technique less flexible than other techniques. Furthermore, one directional shifting is required of the columns and shorts between adjacent Y select lines which do not form pairs cannot be repaired.
A variation on the above technique is implemented in which fuses are located outside the Y decoders and the fuse circuit is similar to that shown in FIG. 2.
Thus, it may be seen that there is a need for a redundancy scheme that eliminates the timing difference between normal and redundant column paths and which reduces the number of fuses and provides greater flexibility in repairing faulty columns.